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Features
* 80C51 Compatible
- Five I/O Ports - Two 16-bit Timer/Counters - 256 Bytes RAM 8K Bytes ROM/OTP Program Memory with 64 Bytes Encryption Array and 3 Security Levels High-Speed Architecture - 33 MHz at 5V (66 MHz Equivalent) - X2 Speed Improvement Capability (6 Clocks/Machine Cycle) 10-bit, 8 Channels A/D Converter Hardware Watchdog Timer with Reset-out Programmable I/O Mode: Standard C51, Input Only, Push-pull, Open Drain Asynchronous Port Reset Full Duplex Enhanced UART with Baud Rate Generator SPI, Master Mode Dual System Clock - Crystal or Ceramic Oscillator (33/40 MHz) - Internal RC Oscillator (12 MHz) - Programmable Prescaler Programmable Counter Array with High-speed Output, Compare/Capture, Pulse Width Modulation and Watchdog Timer Capabilities Interrupt Structure - 8 Interrupt Sources - 4 Interrupt Priority Levels Power Control Modes - Idle Mode - Power-down Mode - Power-off Flag Power Supply: 2.7 - 5.5V Temperature Range: Industrial (-40 To 85C) Package: LQFP48 (Body 7*7*1.4 mm), PLCC52
* * * * * * * * *
8-bit Microcontroller with A/D Converter
* * *
AT80C5112 AT83C5112 AT87C5112
* * *
Description
The AT8xC5112 is a high performance ROM/OTP version of the 80C51 8-bit microcontroller. The AT8xC5112 retains all the features of the standard 80C51 with 8 Kbytes ROM/OTP program memory, 256 bytes of internal RAM, a 8-source, 4-level interrupt system, an on-chip oscillator and two timer/counters. The AT8xC5112 is dedicated for analog interfacing applications. For this, it has a 10bit, 8 channels A/D converter and a five channels Programmable Counter Array. In addition, the AT8xC5112 has a Hardware Watchdog Timer, a versatile serial channel that facilitates multiprocessor communication (EUART) with an independent baud rate generator, a SPI serial bus controller and a X2 speed improvement mechanism. The X2 feature allows to keep the same CPU power at a divided by two oscillator frequency. The fully static design of the AT8xC5112 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.
Rev. 4191B-8051-04/03
The AT8xC5112 has 3 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode, the CPU is frozen while the peripherals are still operating. In the quiet mode, the A/D converter is only operating. In the Power-down mode, the RAM is saved and all other functions are inoperative. Two oscillators source, crystal and RC, provide a versatile power management. The AT8xC5112 is proposed in 48-/52-pin count packages with Port 0 and Port 2 (address/ data buses).
Block Diagram
CEX0-4 RxD TxD Vcc Vss ECI
SPSCK
MISO MOSI
(2) (2) (2) XTAL1 (2) XTAL2
Xtal Osc EUART BRG
(1) (1)
(3)(3) (3) (3)
RAM 256 x8
ROM /OTP
PCA SPI
SS
Watch Dog
8 K *8
C51 CORE
RC Osc
IB-bus
CPU
RST EA ALE PSEN
Timer 0 Timer 1
INT Ctrl
A/D Converter
Parallel I/O Ports Port 1 Port 3 Port 4 Port 0 Port 2
INT0
INT1
AIN0-7
(2) VPP
(2) (3) T0 T1
(2) (3) Vref
(3) P0 P1 P3 P4 P2
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Notes:
1. Alternate function of Port 1. 2. Alternate function of Port 3. 3. Alternate function of Port 4.
2
AT8xC5112
AT8xC5112
SFR Mapping
The Special Function Registers (SFRs) of the AT8xC5112 belongs to the following categories: * * * * * * * * * C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2 Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1 Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1 WatchDog Timer: WDTRST, WDTPRG SPI: SPCON, SPSTA, SPDAT PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF
*
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Table 1. SFR Addresses and Reset Values
0/8 F8h B 0000 0000 CL 0000 0000 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 CMOD X000 0000 1/9 CH 0000 0000 72/A CCAP0H XXXX XXXX ADCLK 0000 0000 CCAP0L XXXX XXXX P1M2 0000 0000 CCAPM0 00XX X000 CCAPM1 X000 0000 3/B CCAP1H XXXX XXXX ADCON 0000 0000 CCAP1L XXXX XXXX 4/C CCAP2H XXXX XXXX ADDL XXXXXX00 CCAP2L XXXX XXXX P3M2 0000 0000 CCAPM2 X000 0000 P1M1 0000 0000 5/D CCAP3H XXXX XXXX ADDH 0000 0000 CCAP3L XXXX XXXX P4M2 0000 0000 CCAPM3 X000 0000 P3M1 0000 0000 CCAPM4 X000 0000 P4M1 0000 0000 6/E CCAP4H XXXX XXXX ADCF 0000 0000 CCAP4L XXXX XXXX CONF 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h
D7h
C8h P4 1111 1111 IPL0 0000 0000 P3 1111 1111 IE0 0000 0000 SADEN 0000 0000 IE1 0000 0000 SADDR 0000 0000 AUXR1 XXXXXXX0 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 TMOD 0000 0000 SP 0000 0111 0/8 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C TH0 0000 0000 TH1 0000 0000 CKSEL XXXX XXX1 5/D OSCCON XXXX XX01 6/E SBUF XXXX XXXX BRL 0000 0000 BDRCON 0000 0000 CKRL 1111 1111 CKCON0 X000X000 PCON 00X1 0000 7/F WDRST 0000 0000 IPL1 0000 0000 IPH1 0000 0000 IPH0 X000 0000 CKCON1 XXXX XXX0 WDTPRG 0000 0000 SPCON 0001 0100 SPSTA XXXXXXXX SPDAT XXXX XXXX
CFh
C0h
C7h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
Reserved
4
AT8xC5112
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AT8xC5112
Pin Configurations
P4.6/AIN6/SPSCK P4.4/AIN4/MISO P4.5/AIN5/MOSI P4.3/AIN3/INT1 P4.2/AIN2/SS P4.1/AIN1/T1 P4.0/AIN0
P4.7/AIN7
P1.0/WR
48 47 46 45 44 43 42 41 40 39 38 37 VREF VSS + AVSS P2.7 P2.6 P2.5 P2.4 P2.3 V2.2 VCC + AVCC P2.1 P2.0 P3.7 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 P3.0/RxD P3.1/TxD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.2/ECI P1.3/CEX0
LQFP48
7*7*1.4 mm
13 14 15 16 17 18 19 20 21 22 23 24
XTAL2 XTAL1 P1.7/CEX4 P1.6/CEX3 ALE PSEN P3.2/INT0 P1.5/CEX2 P1.4/CEX1 VPP P3.6 P3.3/T0
P4.6/AIN6/SPSCK
P4.4/AIN4/MISO
P4.5/AIN5/MOSI
P1.1/RD
RST
EA
P4.3/AIN3/INT1
P4.2/AIN2/SS
P4.1/AIN1/T1
P4.7/AIN7
7 6 5 4 3 2 1 52 51 50 49 48 47
VSS AVSS P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 AVCC + VCC P2.1 P2.0 P3.7 VPP
P4.0/AIN0
P1.0/WR
P1.1/RD
VREF
RST
EA
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
XTAL2 XTAL1 P1.7/CEX4 P1.6/CEX3 ALE PSEN P3.2/INT0 P1.5/CEX2 P1.4/CEX1 P3.4 P3.3/T0 P3.6 P3.5
46 45 44 43 42 41 40 39 38 37 36 35 34
NIC P3.0/RxD P3.1/TxD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.2/ECI P1.3/CEX0
PLCC52
*NIC: No Internal Connection
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Table 2. Pin Description
PIN NUMBER LQFP Mnemonic VSS VCC AVSS AVCC VREF X X 48 X X PLCC 52 X X X I I I I I Name and Function Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle and power-down operation. Analog Ground: 0V reference. Analog Power Supply: This is the power supply voltage for normal and idle operation of the A/D VREF : A/D converter positive reference input. Vpp : Programming Supply Voltage: VPP X X I This pin also receives the 12V programming pulse which will start the EPROM programming and the manufacturer test modes. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. Alternate functions for Port 1 include: I/O I/O I/O I/O I/O I/O I/O I/O P3.0 - P3.7 X X I/O WR (P1.0): External data memory write strobe RD (P1.1): External data memory readstrobe ECI (P1.2): External Clock for the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. P3.6 is an input only pin. Port 3 also serves the special features of the 80C51 family, as listed below. I/O I/O I/O I/O I/O I/O I/O RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 T0 (P3.3): Timer 0 external input Port 4: Port 4 is an 8-bit bi-directional I/O port. Each bit can be set as pure CMOS input or as push-pull output. Port 4 is also the input port of the analog-to-digital converter and used for oscillator and reset. AIN0 (P4.0): A/D converter input 0 AIN1 (P4.1): A/D converter input 1 T1: Timer 1 external input AIN2 (P4.2): A/D converter input 2 SS: Slave select input of the SPI controller AIN3 (P4.3): A/D converter input 3 INT1: External interrupt 1 TYPE
P1.0 - P1.7
X
X
I/O
P4.0-P4.7
X
X
I/O
I/O
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AT8xC5112
Table 2. Pin Description (Continued)
PIN NUMBER LQFP Mnemonic 48 PLCC 52 I/O Name and Function AIN4 (P4.4): A/D converter input 4 MISO: Master IN, Slave OUT of the SPI controller AIN5 (P4.5): A/D converter input 5 MOSI: Master OUT, Slave IN of the SPI controller AIN6 (P4.6): A/D converter input 6 SPSCK: Clock I/O of the SPI controller AIN7 (P4.7): A/D converter input 7 Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX atDPTR). In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX atRi), port 2 emits the contents of the P2 SFR. RST: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR's AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 1FFFH . If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. EA must be held low for ROMless devices. If security level 1 is programmed, EA will be internally latched on Reset. XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 : Output from the inverting oscillator amplifier. TYPE
I/O
I/O I/O P0.0-P0.7 X X I/O
P2.0-P2.7
X
X
I/O
RST
X
X
I
ALE
X
X
O
PSEN
X
X
O
EA
X
X
I
XTAL1 XTAL2
X X
I O
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Clock System
The AT8xC5112 oscillator system provides a reliable clocking system with full mastering of speed versus CPU power trade off. Several clock sources are possible: * * * External clock input High speed crystal or ceramic oscillator Integrated high speed RC oscillator
The selected clock source can be divided by 2-512 before clocking the CPU and the peripherals. When X2 function is set, the CPU needs 6 clock periods per cycle. Clocking is controlled by several SFR registers: OSCON, CKCON0, CKCON1, CKRL.
Blocks Description
The AT8xC5112 includes the following oscillators: * * Crystal oscillator Integrated high speed RC oscillator, with typical frequency of 12 MHz
Crystal Oscillator: OSCA
The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output. Both crystal and ceramic resonators can be used. In oscillator source an XTAL1 is mandatory to start the product. OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the external oscillator input.
Integrated High Speed RC Oscillator: OSCB
The high speed RC oscillator typical frequency is 12 MHz. Note that the on chip oscillator has a 50% frequency tolerance and may not be suitable for use in some applications. OSCBEN in OSCCON register is an enable signal for the high speed RC oscillator.
Clock Selector
CKS bit in CKS register is used to select from crystal to RC oscillator. OSCBEN bit in OSCCON register is used to enable the RC oscillator. OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external oscillator input.
Clock Prescaler
Before supplying the CPU and the peripherals, the main clock is divided by a factor of 2 to 512, as defined by the CKRL register. The CPU needs from 12 to 256*12 clock periods per instruction. This allows: * * to accept any cyclic ratio to be accepted on XTAL1 input. to reduce the CPU power consumption.
The X2 bit allows to bypass the clock prescaler; in this case, the CPU needs only 6 clock periods per machine cycle. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
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AT8xC5112
Functional Block Diagram
Timer 0 clock : 128 ResetB Reload Sub Clock
Ckrl
WD clock
Xtal1 Xtal2 OSCAEN OSCBEN PwdOsc CKS RC_Osc OSCB X2 PwdRC CPU clock Ck Xtal_Osc OSCA 1 A/D clock Mux + Filter OscOut 8-bit Prescaler-Divider 0 1 CkOut CkAdc Peripherals clock CkIdle
0
Quiet Pwd Idle
Operating Modes
Functional Modes Normal Modes * * * CPU and Peripheral clocks depend on the software selection using CKCON0, CKCON1, CKSEL and CKRL registers. CKS bit selects either Xtal_Osc or RC_Osc. CKRL register determines the frequency of the selected clock, unless X2 bit is set. In this case the prescaler/divider is not used, so CPU core needs only 6-clock periods per machine cycle. According to the value of the peripheral X2 individual bit, each peripheral needs 6 or 12 clock period per instructions. It is always possible to switch dynamically by software from Xtal_Osc to RC_Osc, and vice versa by changing CKS bit, a synchronization cell allowing to avoid any spike during transition. IDLE modes are achieved by using any instruction that writes into PCON.0 sfr IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 register: IDLE MODE A: Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1) IDLE MODE B: RC_Osc is running (OSCBEN = 1) and selected (CKS = 0) The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing OSCAEN or OSCBEN respectively. Exit from IDLE mode is achieved by Reset, or by activation of an enabled interrupt. In both cases, PCON.0 is cleared by hardware.
*
Idle Modes
* * * * * * *
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4191B-8051-04/03
*
Exit from IDLE modes will leave the oscillator control bits OSCAEN, OSCBEN and CKS unchanged. POWER DOWN modes are achieved by using any instruction that writes into PCON.1 sfr Exit from POWER DOWN mode is achieved either by a hardware Reset, or by an external interruption. By RST signal: The CPU will restart on OSCA. By INT0 or INT1 interruptions, if enabled. The oscillators control bits OSCAEN, OSCBEN and CKS will not be changed, so the selected oscillator before entering into Power-down will be activated.
Power Down Modes
* * * *
Table 3. Power Modes
PD 0 X 0 X 0 IDLE 0 X 0 X 1 CKS 1 1 0 0 1 OSCBEN X X 1 0 X OSCAEN Selected Mode 1 0 X X 1 Comment
NORMAL MODE A OSCA: XTAL clock INVALID no active clock
NORMAL MODE B OSCB: high speed RC clock INVALID IDLE MODE A The CPU is off, OSCA supplies the peripherics The CPU is off, OSCB supplies the peripherics The CPU is off, OSCA and OSCB are stopped OSCC is stopped
0
1
0
1
X
IDLE MODE B TOTAL POWER DOWN
1
X
X
X
X
Prescaler Divider
* * * * * *
An hardware RESET selects the prescaler divider: CKRL = FFh: internal clock = OscOut/2 (Standard C51 feature) X2 = 0, After Reset, any value between FFh down to 00h can be written by software into CKRL sfr in order to divide frequency of the selected oscillator: CKRL = 00h: minimum frequency = OscOut/512 CKRL = FFh: maximum frequency = OscOut/2
The frequency of the CPU and peripherals clock CkOut is related to the frequency of the main oscillator OscOut by the following formula: FCkOut = FOscOut/(512 - 2*CKRL) Some examples can be found in the table below:
FOscOut MHz 12 12 12 X2 0 0 1 CKRL FF FE x FCkOut (Mhz) 6 3 12
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AT8xC5112
* A software instruction which sets X2 bit de-activates the prescaler/divider, so the internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit.
Timer 0: Clock Inputs
CkIdle T0 pin Sub Clock :6 0 1 C/T TMOD SCLKT0 OSCCON Gate INT0 TR0 0 1 Control Timer 0
The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allow to perform a Real Time Clock function. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode) SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input. When the subclock input is selected for Timer 0 and the crystal oscillator is selected for CPU and peripherals, the CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0 With an external a 32 kHz oscillator, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real Time Clock (RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 KHz most of the time. When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others peripherals.
Registers
Clock Control Register The clock control register is used to define the clock system behavior. Table 4. OSCCON - Clock Control Register (8Fh)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. 5 4 3 2 SCLKT0 1 OSCBEN 0 OSCAEN
6
-
5
-
4
-
11
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Bit Number 3
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Sub Clock Timer0
2
SCLKT0
Cleared by software to select T0 pin Set by software to select T0 Sub Clock Enable RC oscillator This bit is used to enable the high speed RC oscillator 0: The oscillator is disabled 1: The oscillator is enabled. Enable crystal oscillator This bit is used to enable the crystal oscillator 0: The oscillator is disabled 1: The oscillator is enabled.
1
OSCBEN
0
OSCAEN
Reset value = 0XXX X001b Not bit addressable Clock Selection Register The clock selection register is used to define the clock system behavior Table 5. CKSEL - Clock Selection Register (85h)
7 6 Bit Number 7 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Active oscillator selection This bit is used to select the active oscillator 1: The crystal oscillator is selected 0: The high speed RC oscillator is selected. 5 4 3 2 1 0 CKS
6
-
5
-
4
-
3
-
2
-
1
-
0
CKS
Reset value = XXXX XXX 1 b Not bit addressable
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Clock Prescaler Register This register is used to reload the clock prescaler of the CPU and peripheral clock. Table 6. CKRL - Clock prescaler Register (97h)
7 6 5 4 M Bit Number Bit Mnemonic Description 0000 0000b: Division factor equal 512 7: 0 CKRL 1111 1111b: Division factor equal 2 M: Division factor equal 2*(256-M) 3 2 1 0
Reset value = 1111 1111b Not bit addressable Clock Control Register This register is used to control the X2 mode of the CPU and peripheral clock. Table 7. CKCON0 Register (8Fh)
7 Bit Number 7 6 WDX2 Bit Mnemonic Description Reserved Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3 Reserved Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle 5 PCAX2 4 SIX2 3 2 T1X2 1 T0X2 0 X2
6
WdX2
5
PcaX2
4
SiX2
2
T1X2
1
T0X2
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Bit Number
Bit Mnemonic Description CPU clock
0
X2
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.
Reset value = X000 0000b Not bit addressable Table 8. CKCON1 Register (AFh)
7 Bit Number 7 6 5 4 3 2 Bit Mnemonic Description Reserved Reserved Reserved Reserved Reserved Reserved BRG clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle SPI clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle 6 5 4 3 2 1 BRGX2 0 SPIX2
1
BRGX2
0
SPIX2
Reset value = XXXX XX00b Not bit addressable
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Reset and Power Management
The power monitoring and management can be used to supervise the Power Supply (VDD) and to start up properly when AT8xC5112 is powered up. It consists of the features listed below and explained hereafter: * * * * Power-off flag Idle mode Power-down mode Reduced EMI mode
All these features are controlled by several registers, the Power Control register (PCON) and the Auxiliary register (AUXR) detailed at the end of this section. AUX register not available on all versions.
Functional Description
Figure 1 shows the block diagram of the possible sources of microcontroller reset. Figure 1. Reset Sources
RST pin(1)
Hardware WD
Reset RST pin(2)
PCA WD
Notes:
1. RST pin available only on 48 and 52 pins versions. 2. RST pin available only on LPC versions.
Power-off Flag
When the power is turned off or fails, the data retention is not guaranteed. A Power-off Flag (POF, Table 9 on page 16) allows to detect this condition. POF is set by hardware during a reset which follows a power-up or a power-fail. This is a cold reset. A warm reset is an external or a watchdog reset without power failure, hence which preserves the internal memory content and POF. To use POF, test and clear this bit just after reset. Then it will be set only after a cold reset.
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Registers
PCON: Power Configuration Register Table 9. PCON Register (87h)
7 SMOD1 Bit Number 6 SMOD0 Bit Mnemonic 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL
Description Double Baud Rate bit Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in SCON register. SCON Select bit When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write accesses to SCON.6 are to SM1 bit. When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to SCON.6 are to OVR bit. SCON is Serial Port Control register. Reserved Must be cleared. Power-off flag Set by hardware when VDD rises above VRET+ to indicate that the Power Supply has been set off. Must be cleared by software. General Purpose flag 1 One use is to indicate wether an interrupt occurred during normal operation or during Idle mode. General Purpose flag 0 One use is to indicate wether an interrupt occurred during normal operation or during Idle mode. Power-down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
7
SMOD1
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset value = 0000 0000b
Port Pins
The value of port pins in the different operating modes is shown on the figure below. Table 10. Pin Conditions in Special Operating Modes
Mode Reset Idle Power-down Program Memory Don't care Internal Internal Port 1 pins Weak High Data Data Port 3 pins Weak High Data Data Port 4 pins Weak High Data Data
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Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 11. AUXR Register AUXR - Auxiliary Register (8Eh)
7 Bit Number 7 6 Bit Mnemonic 5 4 3 2 1 0 AO
Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches.
6
-
5
-
4
-
3
-
2
-
1
-
0
AO
Reset value = XXXX XXX0b Not bit addressable
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Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle (6 internal clock periods) and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). The T0 bit of the WDTPRG register is used to select the overflow after 10 or 14 bits. When WDT overflows, it will generate an internal reset. It will also drive an output RESET HIGH pulse at the emulator RST-pin. The length of the reset pulse is 24 clock periods of the WD clock. To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC, where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s at FOSC = 12 MHz and T0=0. To manage this feature, refer to WDTPRG register description, Table 13. (SFR0A7h). Table 12. WDTRST Register WDTRST Address (0A6h)
7 Reset value X 6 X 5 X 4 X 3 X 2 X 1 X
Using the WDT
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
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Table 13. WDTPRG Register WDTPRG Address (0A7h)
7 T4 Bit Number 7 6 5 4 6 T3 Bit Mnemonic T4 T3 T2 T1 WDT overflow select bit 3 T0 0: Overflow after 14 bits 1: Overflow after 10 bits 2 1 0 S2 S1 S0 WDT Time-out select bit 2 WDT Time-out select bit 1 WDT Time-out select bit 0 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Selected Time-out with T0=0 (214 - 1) machine cycles, 16.3 ms at 12 MHz (215 - 1) machine cycles, 32.7 ms at 12 MHz (216 - 1) machine cycles, 65.5 ms at 12 MHz (217 - 1) machine cycles, 131 ms at 12 MHz (218 - 1) machine cycles, 262 ms at 12 MHz (219 - 1) machine cycles, 542 ms at 12 MHz (220 - 1) machine cycles, 1.05 s at 12 MHz (221 - 1) machine cycles, 2.09 s at 12 MHz Reserved Do not try to set this bit. 5 T2 4 T1 3 T0 2 S2 1 S1 0 S0
Description
Reset value = XXX0 0000 Write only register WDT During Power Down and Idle Power Down In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as normal whenever the AT8xC5112 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. Idle Mode In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT8xC5112 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
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Ports
All port 1, port 3 and port 4 I/O port pins on the AT8xC5112 may be software configured to one of four types on a bit-by-bit basis, as shown in Table 14. These are: Quasi bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port choose the output type for each port pin. Table 14. Port Output Configuration settings using PxM1 and PxM2 registers
PxM1.y Bit 0 0 1 1 PxM2.y Bit 0 1 0 1 Port Output Mode Quasi bi-directional Push-pull Input-only (High Impedance) Open Drain
Port Types
Quasi bi-directional Output Configuration The default port output configuration for standard AT8xC5112 I/O ports is the Quasi bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open drain output except that there are three pull-up transistors in the Quasi bi-directional output that serve different purposes. One of these pull-ups, called the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The very weak pull-up sources a very small current that will pull the pin high if it is left floating. A second pullup, called the "weak" pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a Quasi bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pullup remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-to-high transitions on a Quasi bi-directional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two CPU clocks, in order to pull the port pin high quickly. Then it turns off again. The Quasi bi-directional port configuration is shown in Figure 2.
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Figure 2. Quasi bi-directional Output
2 CPU CLOCK DELAY
P Strong
P
Very Weak
P Weak
Pin
Port latch Data
N
Input Data
Open Drain Output Configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the Quasi bi-directional mode. The open-drain port configuration is shown in Figure 3.
Figure 3. Open-drain Output
Pin
Port latch Data
N
Input Data
Push-pull Output Configuration
The push-pull output configuration has the same pull-down structure as both the open drain and the Quasi bi-directional output modes, but provides a continuous strong pullup when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. The push-pull port configuration is shown in Figure 4.
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Figure 4. Push-pull Output
P Strong
Pin
Port Latch Data
N
Input Data
Input-only Configuration
The input-only configuration is a pure input with neither pull-up nor pull-down. The input-only configuration is shown in Figure 4. Figure 5. Input-only
Input Data
Pin
Ports Description
Ports P1, P3 and P4 Every output on the AT8xC5112 may potentially be used as a 20 mA sink LED drive output. However, there is a maximum total output current for all ports which must not be exceeded. All ports pins of the AT8xC5112 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times. The inputs of each I/O port of the AT8xC5112 are TTL level Schmitt triggers with hysteresis. Ports P0 and P2 High pin-count version of the AT8xC5112 has standard address and data ports P0 and P2. These ports are standard C51 ports (Quasi bi-directional I/O). The control lines are provided on the pins: ALE, PSEN, EA, Reset; RD and WR signals are on the bits P1.1 and P1.0.
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Registers
Table 15. P1M1 Register P1M1 Address (D4h)
7 P1M1.7 Bit Number 7: 0 6 P1M1.6 5 P1M1.5 Bit Mnemonic P1M1.x Description Port Output configuration bit See Table 10 for configuration definition 4 P1M1.4 3 P1M1.3 2 P1M1.2 1 P1M1.1 0 P1M1.0
Reset value = 0000 00XX Table 16. P1M2 Register P1M2 Address (E2h)
7 P1M2.7 Bit Number 7: 0 6 P1M2.6 5 P1M2.5 Bit Mnemonic P1M2.x Description Port Output configuration bit See Table 10 for configuration definition 4 P1M2.4 3 P1M2.3 2 P1M2.2 1 P1M2.1 0 P1M2.0
Reset value = 0000 00XX Table 17. P3M1 Register P3M1 Address (D5h)
7 P3M1.7 Bit Number 7: 0 6 P3M1.6 5 P3M1.5 Bit Mnemonic P3M1.x Description Port Output configuration bit See Table 10 for configuration definition 4 P3M1.4 3 P3M1.3 2 P3M1.2 1 P3M1.1 0 P3M1.0
Reset value = 0000 0000
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Table 18. P3M2 Register P3M2 Address (E4h)
7 P3M2.7 Bit Number 7: 0 6 P3M2.6 5 P3M2.5 Bit Mnemonic P3M2.x Description Port Output configuration bit See Table 10 for configuration definition 4 P3M2.4 3 P3M2.3 2 P3M2.2 1 P3M2.1 0 P3M2.0
Reset value = 0000 0000 Table 19. P4M1 Register P4M1 Address (D6h)
7 P4M1.7 Bit Number 7: 0 6 P4M1.6 5 P4M1.5 Bit Mnemonic P4M1.x Description Port Output configuration bit See Table 10 for configuration definition 4 P4M1.4 3 P4M1.3 2 P4M1.2 1 P4M1.1 0 P4M1.0
Reset value = 0000 0000 Table 20. P4M2 Register P4M2 Address (E5h)
7 P4M2.7 Bit Number 7: 0 6 P4M2.6 5 P4M2.5 Bit Mnemonic P4M2.x Description Port Output configuration bit See Table 10 for configuration definition 4 P4M2.4 3 P4M2.3 2 P4M2.2 1 P4M2.1 0 P4M2.0
Reset value = 0000 0000
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Dual Data Pointer Register
The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (see Table 21) that allows the program code to switch between them (Refer to Figure 6). Figure 6. Use of Dual Pointer
External Data Memory
7
0 DPS
DPTR1 DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
Table 21. AUXR1: Auxiliary Register 1
7 Bit Number 7 6 5 4 3 2 1 0 DPS
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection Clear to select DPTR0. Set to select DPTR1.
6
-
5
-
4
-
3
-
2
-
1
-
0
DPS
Note:
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
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Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search...) are well served by using one data pointer as a 'source' pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,atDPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX atDPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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Serial I/O Ports Enhancements
The serial I/O ports in the AT8xC5112 are compatible with the serial I/O port in the 80C52. They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O ports include the following enhancements: * * Framing error detection Automatic address recognition
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 7).
Figure 7. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI RI
SCON for UART (98h) (SCON_1 for UART_1 (C0h))
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART) SM0 to UART mode control (SMOD0 = 0 for UART)
SMOD1 SMOD0 POF GF1 GF0 PD IDL
PCON for UART (87h) (SMOD bits for UART_1 are located in BDRCON_1)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 27) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 8. and Figure 9.). Figure 8. UART Timings in Mode 1 RXD Start bit RI SMOD0=X FE SMOD0=1
D0 D1 D2 D3 D4 D5 D6 D7
Data byte
Stop bit
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Figure 9. UART Timings in Modes 2 and 3 D0 D1 D2 D3 RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1
D4
D5
D6
D7
D8
Data byte
Ninth Stop bit bit
Automatic Address Recognition
The automatic address recognition feature is enabled for each UART when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each UART has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don't-care bits (defined by zeros) to form the device's given address. The don't-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb
Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b
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The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.:
SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN1111 111Xb
The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b,
Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b
For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don't-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers.
Baud Rate Selection for UART for mode 1 and 3
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Figure 10. Baud Rate Selection
TIMER1_BRG 0 1 / 16 Rx Clock
INT_BRG RBCK
TIMER1_BRG 0 1 / 16 Tx Clock
INT_BRG TBCK
Table 22. Baud Rate Selection Table for UART
TBCK 0 1 0 1 RBCK 0 0 1 1 Clock Source for UART Tx Timer 1 INT_BRG Timer 1 INT_BRG Clock Source UART Rx Timer 1 Timer 1 INT_BRG INT_BRG
Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the X2 bit in CKON0 register, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register (for UART) : Figure 11. Internal Baud Rate Generator
SMOD1 /2 0 auto reload counter Peripheral clock /6 0 1 BRL SPD BRR BRG overflow 1 INT_BRG
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for UART: Baud_Rate = 2SMOD1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)] 2SMOD1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x Baud_Rate Example of computed value when X2=1, SMOD1=1, SPD=1
Baud Rates FXTAL = 16.384 MHz BRL 115200 57600 38400 28800 19200 9600 4800 247 238 229 220 203 149 43 Error (%) 1.23 1.23 1.23 1.23 0.63 0.31 1.23 BRL 243 230 217 204 178 100 FXTAL = 24 MHz Error (%) 0.16 0.16 0.16 0.16 0.16 0.16 -
(BRL) = 256 -
Example of computed value when X2=0, SMOD1=0, SPD=0
Baud Rates FOSC = 16.384 MHz BRL 4800 2400 1200 600 247 238 220 185 Error (%) 1.23 1.23 1.23 0.16 BRL 243 230 202 152 FOSC = 24 MHz Error (%) 0.16 0.16 3.55 0.16
The baud rate generator can be used for mode 1 or 3 (refer to Figure 10. ), but also for mode 0 for both UARTs, thanks to the bit SRC located in BDRCON register (see Table 29).
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UART Registers
Table 23. SADEN - Slave Address Mask Register for UART (B9h)
7 6 5 4 3 2 1 0
Reset value = 0000 0000b Table 24. SADDR - Slave Address Register for UART (A9h)
7 6 5 4 3 2 1 0
Reset value = 0000 0000b Table 25. SBUF - Serial Buffer Register for UART (99h)
7 6 5 4 3 2 1 0
Reset value = XXXX XXXXb Table 26. BRL - Baud Rate Reload Register for the internal baud rate generator, UART UART(9Ah)
7 6 5 4 3 2 1 0
Reset value = 0000 0000b
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Table 27. SCON Register SCON - Serial Control Register for UART (98h)
7 FE/SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) for UART Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 (SMOD0=0) for UART Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit Serial port Mode bit 1 for UART SM0 SM1 Mode Description Baud Rate 6 SM1 0 0 1 1 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART FXTAL/12 (FXTAL/6 X2 mode) Variable FXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode) Variable
7
FE
SM0
5
SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit for UART Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. Reception Enable bit for UART Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 for UART.
4
REN
3
TB8
Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8/Ninth bit received in modes 2 and 3 for UART Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Transmit Interrupt flag for UART Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag for UART Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 8. and Figure 9. in the other modes.
2
RB8
1
TI
0
RI
Reset value = 0000 0000b Bit addressable
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Table 28. PCON Register PCON - Power Control Register (87h)
7 SMOD1 Bit Number 7 6 SMOD0 5 RSTD 4 POF 3 GF1 2 GF0 1 PD 0 IDL
Bit Mnemonic Description SMOD1 Serial port Mode bit 1 for UART Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 for UART Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. Reset Detector Disable Bit
6
SMOD0
5
RSTD
Clear to disable PFD. Set to enable PFD. Power-off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-down mode bit Cleared by hardware when reset occurs. Set to enter Power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode.
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset value = 0001 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn't affect the value of this bit.
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Table 29. BDRCON Register BDRCON - Baud Rate Control Register (9Bh)
7 Bit Number 7 6 Bit Mnemonic 5 4 BRR 3 TBCK 2 RBCK 1 SPD 0 SRC
Description Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run Control bit Clear to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Transmission Baud rate Generator Selection bit for UART Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Reception Baud Rate Generator Selection bit for UART Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Baud Rate Speed Control bit for UART Clear to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART
6
-
5
-
4
BRR
3
TBCK
2
RBCK
1
SPD
0
SRC
Clear to select FOSC/12 as the Baud Rate Generator (FOSC/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset value = XXX0 0000b
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Serial Port Interface (SPI)
Features
The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI module include the following: * * * * * * Full-duplex, three-wire synchronous transfers Master operation Eight programmable Master clock rates Serial clock with programmable polarity and phase Master Mode fault error flag with MCU interrupt capability Write collision flag protection
Signal Description
Figure 12 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices: Figure 12. Typical SPI bus
MISO MOSI SCK SS 0 1 2 3 Slave 1 MISO MOSI SCK SS
VDD
Master
PORT
MISO MOSI SCK SS
Slave 4
MISO MOSI SCK SS
Slave 3
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB)last. This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines. Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port
Master Input Slave Output (MISO)
SPI Serial Clock (SCK)
Slave Select (SS)
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MISO MOSI SCK SS
AT8xC5112
pins (Figure 12). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (See Error Conditions). Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock. Table 30 gives the different clock rates selected by SPR2:SPR1:SPR0: Table 30. SPI Master Baud Rate Selection
SPR2:SPR1:SPR0 000 001 010 011 100 101 110 111 Clock Rate FCkIdle /2 FCkIdle /4 FCkIdle/8 FCkIdle/16 FCkIdle /32 FCkIdleH /64 FCkIdle /128 External clock Baud Rate Divisor (BD) 2 4 8 16 32 64 128 Output of BRG
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Functional Description
Figure 13 shows a detailed structure of the SPI module. Figure 13. SPI Module Block Diagram
Internal Bus SPDAT CkIdle Shift Register
7 6 5 4 3 2 1 0
Clock Divider
/2 /4 /8 /16 /32 /64 /128
Receive Data Register
Pin Control Logic
M S
MOSI MISO
External Clk
Clock Select
Clock Logic
SCK SS
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI Interrupt Request
SPI Control
8-bit bus 1-bit signal
SPSTA
SPIF WCOL
-
MODF
-
-
-
-
Operating Modes
The Serial Peripheral Interface can be configured as Master mode only. The configuration and initialization of the SPI module is made through one register: * * * * The Serial Peripheral CONtrol register (SPCON) SPCON The Serial Peripheral STAtus register (SPSTA) The Serial Peripheral DATa register (SPDAT) Once the SPI is configured, the data exchange is made using:
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 14).
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Figure 14. Full-Duplex Master-slave Interconnection
8-bit Shift register
MISO MOSI
MISO MOSI SCK
8-bit Shift register
SPI Clock Generator
SCK SS VDD
SS VSS
Master MCU
Slave MCU
Master Mode
The SPI operates in Master mode. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from the Slave on the Master's MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. When the pin SS is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the SPDAT is present.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock POLarity (CPOL (1) ) and the Clock PHAse (CPHA(1)). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 15 and Figure 16). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
Figure 15. Data Transmission Format (CPHA = 0)
SCK cycle number SPEN (internal)
1 2 3 4 5 6 7 8
SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB
1.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = '0').
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Figure 16. Data Transmission Format (CPHA = 1)
SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB 1 2 3 4 5 6 7 8
As shown in Figure 15, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 17). Figure 17. CPHA/SS timing
MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Byte 1 Byte 2 Byte 3
Figure 16 shows an SPI transmission in which CPHA is '1'. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 17). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line.
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Error Conditions Mode Fault (MODF) The following flags in the SPSTA signal SPI error conditions: MODe Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: * * * An SPI receiver/error CPU interrupt request is generated. The SPEN bit in SPCON is cleared. This disables the SPI. The MSTR bit in SPCON is cleared.
The MODF flag is set when the SS signal becomes '0'. However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master is attempting to drive the network. In this case, c learing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. Overrun Condition An overrun condition occurs when the Master device tries to send several data bytes and the Slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost. This condition is not detected by the SPI peripheral. Interrupts Two SPI status flags can generate a CPU interrupt request: Table 31. SPI Interrupts
Flag SPIF (SP data transfer) MODF (Mode Fault) Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = '0')
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF generates receiver/error CPU interrupt requests.
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Figure 18 gives a logical view of the above statements: Figure 18. SPI Interrupt Requests Generation
SPIF SPI Transmitter CPU Interrupt Request SPI Receiver/error CPU Interrupt Request SSDIS SPI CPU Interrupt Request
MODF
Registers
There are three registers in the module that provide control, status and data storage functions. These registers are described in the following paragraphs. The Serial Peripheral Control Register does the following: * * * Selects one of the Master clock rates, Selects serial clock polarity and phase, Enables the SPI module.
Serial Peripheral Control Register (SPCON)
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Table 32 describes this register and explains the use of each bit: Table 32. Serial Peripheral Control Register
7 SPR2 Bit Number 7 6 SPEN Bit Mnemonic SPR2 5 - 4 - 3 CPOL 2 CPHA 1 SPR1 0 SPR0
R/W Mode RW
Description Serial Peripheral Rate 2 Bit with SPR1 and SPR0 define the clock rate Serial Peripheral Enable
6
SPEN
RW
Clear to disable the SPI interface Set to enable the SPI interface
5
-
RW
Reserved Leave this Bit at 0. Reserved Leave this Bit at 1. Clock Polarity
4
-
RW
3
CPOL
RW
Clear to have the SCK set to '0' in idle state Set to have the SCK set to '1' in idle low Clock Phase
2
CPHA
RW
Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL) Set to have the data sampled when the SPSCK returns to idle state (see CPOL) Serial Peripheral Rate (SPR2:SPR1:SPR0) 000: FCkIdle /2
1
SPR1
RW
001: FCkIdle /4 010: FCkIdle /8 011: FCkIdle /16 100: FCkIdle /32
0
SPR0
RW
101: FCkIdle /64 110: FCkIdle /128 111: External clock, output of BRG
Reset value = 00010100b Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: * * * Data transfer complete Write collision Inconsistent logic level on SS pin (mode fault error)
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Table 33 describes the SPSTA register and explains the use of every bit in the register: Table 33. Serial Peripheral Status and Control Register
7 SPIF Bit Number 6 WCOL Bit Mnemonic 5 R/W Mode 4 MODF 3 2 1 0 -
Description Serial Peripheral data transfer flag
7
SPIF
R
Cleared by hardware to indicate data that transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. Write Collision flag
6
WCOL
R
Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected.
5
-
RW
Reserved The value read from this bit is indeterminate. Do not set this bit Mode Fault
4
MODF
R
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level
3
-
RW
Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit
2
-
RW
1
-
RW
0
-
RW
Reset value = 00X0XXXXb Serial Peripheral Data Register (SPDAT) The Serial Peripheral Data Register (Table 34) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model. A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register.
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Table 34. Serial Peripheral Data Register
7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0
Reset value = XXXX XXXXb R7:R0: Receive data bits SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: * * * * * Do not change SPR2, SPR1 and SPR0 Do not change CPHA and CPOL Do not change MSTR Clearing SPEN would immediately disable the peripheral Writing to the SPDAT will cause an overflow
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Analog-to-Digital Converter (ADC)
This section describes the on-chip 10-bit analog-to-digital converter of the T89C51RB2/RC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC to select one of the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cascaded potentiometric ADC. Three kind of conversions are available: * * * Standard conversion (7-8 bits). Precision conversion (8-9 bits). Accurate conversion (10 bits).
For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start the conversion. The chip is in a pseudo-idle mode, the CPU doesn't run but the peripherals are always running. This mode allows digital noise to be lower, to ensure precise conversion. For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start the conversion. The chip is in a quiet mode, the AD is the only peripheral running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended.
Features
* * * * * * * * * *
8 channels with multiplexed inputs 10 - bit cascaded potentiometric ADC Conversion time down to 10 micro-seconds Zero Error (offset) +/- 2 LSB max External Positive Reference Voltage Range 2.4 to Vcc ADCIN Range 0 to Vcc Integral non-linearity typical 1 LSB, max. 2 LSB (with 0.9*VccADC I/O Functions
AINx are general I/O that are shared with the ADC channels. The channel select bits in ADCF register define which ADC channel pin will be used as ADCIN. The remaining ADC channels pins can be used as general purpose I/O or as the alternate function that is available. Writes to the port register which aren't selected by the ADCF will not have any effect.
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Figure 19. ADC Description
ADCON.5 ADCON.3
ADEN
ADSST
ADCON.4
ADEOC
CONV_CK
CONTROL
ADC Interrupt Request EADC
IE1.1
AIN0/P4.0 AIN1/P4.1 AIN2/P4.2 AIN3/P4.3 AIN4/P4.4 AIN5/P4.5 AIN6/P4.6 AIN7/P4.7
000 001 010 011 100 101 110 111
AVSS
ADCIN
8
+ SAR 2
ADDH ADDL
Sample and Hold R/2R DAC
10
ADCON.5
VAGND
SCH2
ADCON.2
SCH1
ADCON.1
SCH0
ADCON.0
ADEN
VADREF
Vref
Figure 20 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and does not provide precise timing information. For ADC characteristics and timing parameters refer to the Section "AC Characteristics" of the AT8xC5112 datasheet. Figure 20. Timing Diagram CONV_CK ADEN
TSETUP
ADSST
TCONV
ADEOC
Note: Tsetup = 4 us
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ADC Operation
Before starting a conversion, the A/D converter must be enabled, by setting the ADEN bit, for at least Tsetup (four microseconds). A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). From the ADSST set, the first full CONV_CK period will be the sampling period for the ADC; during this period, the switch is closed and the capacitor is being charged. At the end of the first period, the switch opens and the capacitor is no longer being charged. During the next 10 CONV_CK periods, the sample and hold will be in hold mode during the conversion. The busy flag ADSST(ADCON.3) remains set as long as an A/D conversion is running. After completion of the A/D conversion, it is cleared by hardware. When a conversion is running, this flag can be read only, a write has no effect. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it is cleared by software. If the bit EADC (IE1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 22). Clear this flag for re-arming the interrupt. From this point, if you keep starting a new conversion by resetting ADSST without changing ADEN, it is not necessary to wait Tsetup. The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Before starting normal power reduction modes the ADC conversion has to be completed. Table 35. Selected Analog Input
SCH2 0 0 0 0 1 1 1 1 SCH1 0 0 1 1 0 0 1 1 SCH0 0 1 0 1 0 1 0 1 Selected Analog Input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND. Note that ADCIN should not exceed VAREF absolute maximum range.
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Clock Selection
The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in the AC characteristics section. A prescaler is featured (ADCCLK) to generate the CONV_CK clock from the oscillator frequency. Figure 21. A/D Converter Clock
CONV_CK CKADC
/2
Prescaler ADCLK A/D Converter
The conversion frequency CONV_CK is derived from the oscillator frequency with the following formulas : FCkAdc = FOscOut/(512 - 2*CKRL) , if X2=0 = FOscOut and FCONV_CK = FCkAdc/(2*PRS), if PRS > 0 FCONV_CK = FCkAdc/256, if PRS = 0 Some examples can be found in the table below: , if X2=1
ADC Standby Mode
FOscOut MHz 16 16 X2 0 1 CKRL FF NA FCkAdc Mhz 8 16 ADCLK 12 32 FCONV_CK khz 333 250 Conversion time s 33 44
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode the power dissipation is about 1W.
Voltage Reference
The Vref pin is used to enter the voltage reference for the A/D conversion. Best accuracy is obtained with 0.9 Vcc < Vref < Vcc.
IT ADC Management
An interrupt end-of-conversion will occur when the bit ADEOC is activated and the bit EADC is set. To re-arm the interrupt the bit ADEOC must be cleared by software. Figure 22. ADC Interrupt Structure
ADEOC
ADCON.2
ADCI EADC
IE1.1
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Registers
Table 36. ADCON Register ADCON (S:F3h) ADC Control Register
7 QUIETM Bit Number 6 PSIDLE 5 ADEN 4 ADEOC 3 ADSST 2 SCH2 1 SCH1 0 SCH0
Bit Mnemonic
Description Pseudo Idle mode (best precision) Set to put in quiet mode during conversion. Cleared by hardware after completion of the conversion. Pseudo Idle mode (good precision) Set to put in idle mode during conversion. Cleared by hardware after completion of the conversion. Enable/Standby Mode Set to enable ADC. Clear for Standby mode (power dissipation 1 uW). End Of Conversion Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software. Start and Status Set to start an A/D conversion. Cleared by hardware after completion of the conversion. Selection of channel to convert see Table 35.
7
QUIETM
6
PSIDLE
5
ADEN
4
ADEOC
3
ADSST
2-0
SCH2:0
Reset value = X000 0000b Table 37. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler
7 Bit Number 7 6 PRS 6 5 PRS 5 4 PRS 4 3 PRS 3 2 PRS 2 1 PRS 1 0 PRS 0
Bit Mnemonic -
Description Reserved Leave this bit at 0. Clock Prescaler fCONV_CK = fCkADC/(2 * PRS) if PRS=0, fCONV_CK = fCkADC/256
6-0
PRS6:0
Reset value = 0000 0000b
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Table 38. ADDH Register ADDH (S:F5h Read Only) ADC Data High byte register
7 ADAT 9 Bit Number 7-0 6 ADAT 8 5 ADAT 7 4 ADAT 6 3 ADAT 5 2 ADAT 4 1 ADAT 3 0 ADAT 2
Bit Mnemonic Description ADAT9:2 ADC result bits 9 - 2
Read only register Reset value = 00h Table 39. ADDL Register ADDL (S:F4h Read Only) ADC Data Low byte register
7 Bit Number 7-6 6 Bit Mnemonic 5 Description Reserved The value read from these bits are indeterminate. Do not set these bits. ADC result bits 1 - 0 4 3 2 1 ADAT 1 0 ADAT 0
1-0
ADAT1:0
Read only register Reset value = xxxx xx00b Table 40. ADCF Register ADCF (S:F6h) ADC Input Select Register
7 SEL7 6 SEL6 5 SEL5 4 SEL4 3 SEL3 2 SEL2 1 SEL1 0 SEL0
Bit Number Bit Mnemonic Description Select Input 7 - 0 Set to select bit 7 - 0 as possible input for A/D Cleared to leave this bit free for other function
7-0
SEL7 - 0
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Programmable Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals: * * * * * * * * Oscillator frequency / 12 (/ 6 in X2 mode) Oscillator frequency / 4 (/ 2 in X2 mode) Timer 0 overflow External input on ECI (P1.2) rising and/or falling edge capture software timer high-speed output, or pulse width modulator
Each compare/capture modules can be programmed in any one of the following modes:
Module 4 can also be programmed as a watchdog timer (See Section "PCA PWM Mode", page 61). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O.
PCA Component 16-bit Counter 16-bit Module 0 16-bit Module 1 16-bit Module 2 16-bit Module 3 16-bit Module 4 External I/O Pin P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4
The PCA timer is a common time base for all five modules (See Figure 23). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 41) and can be programmed to run at: * * * * 1/12 the oscillator frequency. (Or 1/6 in X2 Mode) 1/4 the oscillator frequency. (Or 1/2 in X2 Mode) The Timer 0 overflow. The input on the ECI pin (P1.2).
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Figure 23. PCA Timer/Counter
To PCA modules Fosc /12 Fosc/4 T0 OVF P1.2 CH CL 16 bit up/down counter overflow It
CIDL Idle
WDTE
CPS1 CPS0
ECF
CMOD 0xD9
CF
CR
CCF4 CCF3
CCF2 CCF1
CCF0
CCON 0xD8
Table 41. CMOD: PCA Counter Mode Register: CMOD Address 0D9H
7 CIDL Bit Number 7 6 WDTE Bit Mnemonic CIDL 5 4 3 2 CPS1 1 CPS0 0 ECF
Description Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. Not implemented, reserved for future use. (1) Not implemented, reserved for future use. Not implemented, reserved for future use. CPS1 0 CPS0 0 1 0 1 Selected PCA input (2) Internal clock fosc/12 ( Or fosc/6 in X2 Mode). Internal clock fosc/4 ( Or fosc/2 in X2 Mode). Timer 0 Overflow External clock at ECI/P1.2 pin (max rate = fosc/ 8)
6 5 4 3
WDTE -
2
CPS1
0 1 1
1 0
CPS0 ECF
PCA Count Pulse Select bit 0. PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.
Reset value = 00XXX00
1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
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2.
fosc = oscillator frequency
The CMOD SFR includes three additional bits associated with the PCA (See Figure 23 and Table 41). * * * The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the watchdog function on module 4. The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 42). * * Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software.
*
Table 42. CCON: PCA Counter Control Register CCON Address OD8H
7 CF Bit Number 6 CR 5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 0 CCF0
Bit Mnemonic Description PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. Not implemented, reserved for future use. (1) PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
7
CF
6 5 4
CR CCF4
3
CCF3
2
CCF2
1
CCF1
0
CCF0
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
The watchdog timer function is implemented in module 4 (See Figure 26).
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The PCA interrupt system is shown in Figure 24 below. Figure 24. PCA Interrupt System
CF PCA Timer/Counter CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8
Module 0
Module 1
To Interrupt priority decoder
Module 2
Module 3
Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IE.6 EC IE.7 EA
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: * * * * * * 16-bit Capture, positive-edge triggered, 16-bit Capture, negative-edge triggered, 16-bit Capture, both positive and negative-edge triggered, 16-bit Software Timer, 16-bit High Speed Output, 8-bit Pulse Width Modulator.
In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 43). The registers contain the bits that control the mode that each module will operate in. * The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition.
* *
*
*
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*
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 43 shows the CCAPMn settings for the various PCA functions. Table 43. CCAPMn: PCA Modules Compare/Capture Control Registers CAPMn Address n = 0 - 4
7 Bit Number 7 6 5 4 6 ECOMn Bit Mnemonic ECOMn CAPPn CAPNn 5 CAPPn 4 CAPn 3 MATn 2 TOGn 1 PWMm 0 ECCFn
Description Not implemented, reserved for future use. (1) Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.
3
MATn
2
TOGn
1
PWMn
0
ECCFn
Reset value = X000000
1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Table 44. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn 0 X 0 1 CAPNn 0 0 MATn 0 0 TOGn 0 0 PWMm 0 0 ECCFn Module Function 0 X No Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer/Compare mode. 16-bit High Speed Output 8-bit PWM Watchdog Timer (module 4 only)
X
0
1
0
0
0
X
X
1
1
0
0
0
X
1 1 1 1
0 0 0 0
0 0 0 0
1 1 0 1
0 1 0 X
0 0 1 0
X X 0 X
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There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table & Table 46) Table 45. CCAPnH: PCA Modules Capture/Compare Registers High
CCAPnH Address n=0-4 CCAP0H=0FAH CCAP1H=0FBH CCAP2H=0FCH CCAP3H=0FDH CCAP4H=0FEH 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 46. CCAPnL: PCA Modules Capture/Compare Registers Low
CCAPnL Address n=0-4 CCAP0L=0EAH CCAP1L=0EBH CCAP2L=0ECH CCAP3L=0EDH CCAP4L=0EEH 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 47. CH: PCA Counter High
CH Address 0F9H 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 48. CL: PCA Counter Low
CL Address 0E9H 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
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PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 25).
Figure 25. PCA Capture Mode
CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA IT
PCA Counter/Timer Cex.n Capture CH CL
CCAPnH
CCAPnL
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE
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16-bit Software Timer/ Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 26).
Figure 26. PCA Compare Mode and PCA Watchdog Timer
CCON CF Write to CCAPnL Write to CCAPnH 1 0 Enable 16 bit comparator RESET (1) Reset PCA IT CCAPnH CCAPnL Match CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
CH
CL
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4 0xDA to 0xDE
CIDL
WDTE
CPS1 CPS0
ECF
CMOD 0xD9
Note:
1. Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could occur. Writing to CCAPnH will set the ECOM bit. Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
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High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 27). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. Figure 27. PCA High Speed Output Mode
CCON CF CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
Write to CCAPnL Reset
PCA IT Write to CCAPnH 0 CCAPnH Enable 16 bit comparator CCAPnL Match
1
CH
CL
CEXn
PCA counter/timer CCAPMn, n = 0 to 4
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
0xDA to 0xDE
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 28 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than, the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
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Figure 28. PCA PWM Mode
CCAPnH Overflow
CCAPnL "0" Enable 8 bit comparator CEXn
< >
"1"
CL PCA counter/timer
ECOMn CAPPn CAPNn
MATn
TOGn
PWMn ECCFn
CCAPMn, n= 0 to 4 0xDA to 0xDE
An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 26 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: * * * periodically change the compare value so it will never match the PCA timer periodically change the PCA timer value so it will never match the compare values or disable the watchdog by clearing the WDTE bit before a match occurs and then reenable it.
The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won't generate a reset out on the reset pin.
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ROM
ROM Structure
The T83C5112 ROM memory is divided in three different arrays: * * * the code array: 8K bytes the encryption array: 64 bytes the signature array: 4 bytes
ROM Lock System
Encryption Array
The program Lock system, when programmed, protects the on-chip program against software piracy. Within the ROM array are 64 bytes of encryption array. Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR'ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values.
Program Lock Bits
The lock bits when programmed according to Table 41. will provide different level of protection for the on-chip code and data.
Program Lock Bits Security level
LB1
LB2
Protection Description No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset. Same as 2, also verify is disabled
1
U
U
2
P
U
3
U
P
This security level is available because ROM integrity will be verified thanks to another method.
U: unprogrammed P: programmed Signature Bytes The T83C5112 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in Section "Signature Bytes", page 72. Refer to Section "Verify Algorithm", page 74.
Verify Algorithm
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Interrupt System
The AT8xC5112 has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (timers 0, 1), serial port interrupt, PCA, SPI and A/D. These interrupts are shown in Figure 29.
Figure 29. Interrupt Control System
IPH, IP 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 TF1 0 CF Interrupt polling sequence High priority interrupt
PCA
CCFx RI TI
3 0 3 0
NC
3 0 3
SPI 0 3 ADC 0
Individual enable
Global disable
Low priority interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 51). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 53) and in the Interrupt Priority High register (See Table 55). Table 49 shows the bit values and priority levels associated with each combination.
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Table 49. Priority Bit Level Values
IPH.x 0 0 1 1 IP.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 50. Address Vectors
Interrupt Name external interrupt (INT0) Timer0 (TF0) external interrupt (INT1) Timer1 (TF1) PCA (CF or CCFn) UART (RI or TI) SPI ADC Interrupt Address Vector 0003h 000Bh 0013h 001Bh 0033h 0023h 004Bh 0043h Priority Number 1 2 3 4 5 6 8 9
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Table 51. IE0 Register IE0 - Interrupt Enable Register (A8H)
7 EA Bit Number 6 EC Bit Mnemonic 5 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. PCA Interrupt Enable Clear to disable the the PCA interrupt. Set to enable the the PCA interrupt. Reserved The value read from this bit is indeterminate. Do not set this bit. Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.
7
EA
6
EC
5
-
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Reset value = 00X0 0000b Bit addressable
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Table 52. IE1 Register IE1 (S:B1H) - Interrupt Enable Register
7 Bit Number 7 6 5 4 3 2 ESPI 1 EADC 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Enable bit Clear to disable the SPI interrupt. Set to enable the SPI interrupt. A/D Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. Reserved The value read from this bit is indeterminate. Do not set this bit.
6
-
5
-
4
-
3
-
2
ESPI
1
EADC
0
-
Reset value = XXXX X00Xb No Bit addressable
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Table 53. IPL0 Register IPL0 - Interrupt Priority Register (B8H)
7 Bit Number 7 6 PPC Bit Mnemonic 5 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Counter Interrupt Priority bit Refer to PPCH for priority level Reserved The value read from this bit is indeterminate. Do not set this bit. Serial port Priority bit Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level.
6
PPC
5
-
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Reset value = X0X0 0000b Bit addressable.
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Table 54. IPL1 Register IPL1 - Interrupt Priority Low Register 1 (S:B2H)
7 Bit Number 7 6 5 4 3 2 PSPI 1 PADC 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority level less significant bit. Refer to PSPIH for priority level. ADC Interrupt Priority level less significant bit. Refer to PADCH for priority level. Reserved The value read from this bit is indeterminate. Do not set this bit.
6
-
5
-
4
-
3
-
2
PSPI
1
PADC
0
-
Reset value = XXXX X00Xb Not Bit addressable.
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Table 55. IPH0 Register IPH0 - Interrrupt Priority High Register
7 Bit Number 7 6 PPCH 5 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Counter Interrupt Priority level most significant bit PPCH PPC 0 1 0 1 Highest Priority Level Lowest 0 0 1 1
6
PPCH
5
-
Reserved The value read from this bit is indeterminate. Do not set this bit. Serial port Priority High bit PS Priority Level PSH
4
PSH
0 0 1 1
0 1 0 1
Lowest
Highest
Timer 1 overflow interrupt Priority High bit PT1H 3 PT1H 0 0 1 1 PT1 0 1 0 1 Highest Priority Level Lowest
External interrupt 1 Priority High bit PX1 Priority Level PX1H 2 PX1H 0 0 1 1 0 1 0 1 Highest Lowest
Timer 0 overflow interrupt Priority High bit PT0H 1 PT0H 0 0 1 1 PT0 0 1 0 1 Highest Priority Level Lowest
External interrupt 0 Priority High bit PX0H 0 PX0H 0 0 1 1 PT0 0 1 0 1 Highest Priority Level Lowest
Reset value = X0X0 0000b Not bit addressable
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Table 56. IPH1 Register IPH1 - Interrupt High Register 1 (B3H)
7 Bit Number 7 6 5 4 3 2 PSPIH 1 PADCH 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority level most significant bit PSP1H PSP1 0 1 0 1 Highest Priority Level Lowest 0 0 1 1
6
-
5
-
4
-
3
-
2
PSPIH
ADC Interrupt Priority level most significant bit PADCH 1 PADCH 0 0 1 1 0 PADC 0 1 0 1 Highest Priority Level Lowest
Reserved The value read from this bit is indeterminate. Do not set this bit.
Reset value = XXXX X00Xb Not bit addressable
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EPROM
EPROM Structure
The T87C5112 EPROM is divided into two different arrays: * * * the code array: 8K bytes the encryption array: 64 bytes the signature array: 4 bytes
In addition a third non programmable array is implemented:
EPROM Lock System
Encryption Array
The program Lock system, when programmed, protects the on-chip program against software piracy. Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF's). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusiveNOR'ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values.
Program Lock Bits
The three lock bits located in the CONF byte, when programmed according to Table will provide different levels of protection for the on-chip code and data.
Table 57. Program Lock Bits
Program Lock Bits Security level LB1 LB2 LB3 Protection Description No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled 3 U P U This security level is available because ROM integrity will be verified thanks to another method. Same as 3, also external execution is disabled.
1
U
U
U
2
P
U
U
4
U
U
P
U: unprogrammed P: programmed WARNING: Security level 2 and higher should only be programmed after EPROM verification.
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Configuration Byte
The configuration byte is a special register. Its content is defined by the diffusion mask in the ROM version or is read or written by the OTP programmer in the OTP version. This register can also be accessed as a read only register. Table 58. CONF - Configuration Byte (EFh)
7 LB1 Bit Number 7:5 6 LB2 5 LB3 4 1 3 1 2 1 1 1 0 1
Bit Mnemonic Description Program memory lock bits See previous chapter for the definition of these bits. Reserved Leave this bit at 1. Reserved Leave this bit at 1. Reserved Leave this bit at 1. Reserved Leave this bit at 1. Reserved Leave this bit at 1.
4
3
-
2
-
1
-
0
-
Reset value = 1111 111X Signature Bytes The T87C5112 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in Section .
EPROM Programming
Set-up Modes In order to program and verify the EPROM or to read the signature bytes, the T87C5112 is placed in specific set-up modes (See Figure 30.). Control and program signals must be held at the levels indicated in Definition of Terms Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4, P3.5 respectively for A0-A15 (P2.5 (A13) for RB, P3.4 (A14) for RC, P3.5 (A15) for RD) Data Lines:P0.0-P0.7 for D0-D7 Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. Program Signals:ALE/PROG, RST/VPP.
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Table 59. EPROM Set-up Modes
Mode Program Code data RST 1 PSEN 0 ALE/PR OG RST/VPP 12.75V P2.6 0 P2.7 1 P3.3 1 P3.6 1 P3.7 1
Verify Code data
1
0
1
1
0
0
1
1
Program Encryption Array Address 0-3Fh
1
0
12.75V
0
1
1
0
1
Read Signature Bytes
1
0
1
1
0
0
0
0
Program Lock bit 1
1
0
12.75V
1
1
1
1
1
Program Lock bit 2
1
0
12.75V
1
1
1
0
0
Program Lock bit 3
1
0
12.75V
1
0
1
1
0
Program CONF byte
1
0
12.75V
1
0
1
0
0
Read CONF byte
1
0
1
1
0
0
0
1
Figure 30. Set-up Modes Configuration
+5V PROGRAM SIGNALS* +5V RST/VPP ALE/PROG EA RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 XTAL1 P0.0-P0.7 D0-D7 VCC
P1.0-P1.7 P2.0-P2.5 P3.4-P3.5
A0-A7 A8-A15
CONTROL SIGNALS*
4 to 6 MHz
VSS GND
* See for proper value on these inputs
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Programming Algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. To program the AT8xC5112 the following sequence must be exercised: * * * * * * Step 1: Activate the combination of control signals. Step 2: Input the valid address on the address lines. Step 3: Input the appropriate data on the data lines. Step 4: Raise RST/VPP from VCC to VPP (typical 12.75V). Step 5: Pulse ALE/PROG once. Step 6: Lower RST/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 31). Programming CONF Byte After having apply the proper test mode, algorithm for programming CONF byte is similar to the previous programming algorithm with no address to present on the address lines. Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the T87C5112. P 2.7 is used to enable data output. To verify the T87C5112 code the following sequence must be exercised: * * * Step 1: Activate the combination of program and control signals. Step 2: Input the valid address on the address lines. Step 3: Read data on the data lines.
Verify Algorithm
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 31). The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. Verify CONF Byte After having apply the proper test mode, algorithm for read/verify CONF byte is similar to the previous verify algorithm with no address to present on the address lines. Figure 31. Programming and Verification Signal's Waveform
Programming Cycle A0-A12 D0-D7 Data In Data Out Read/Verify Cycle
100s
ALE/PROG 12.75V 5V 0V
RST/VPP Control signals
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Signature Bytes
Signature Bytes Content The T87C5112 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure for EPROM verify but activate the control lines provided in xxxx for Read Signature Bytes. Table 60. shows the content of the signature byte for theT87C5112. Table 60. Signature Bytes Content
Location 30h 31h 60h Contents 58h 57h 2Dh Comment Manufacturer Code: Atmel Family Code: C51 X2 Product name: AT8xC5112 8K ROM version Product name: AT8xC5112 8K OTP version Product revision number: AT8xC5112 Rev.0
60h
ADh
61h
EFh
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Electrical Characteristics
Absolute Maximum Ratings
C = commercial..................................................... 0C to 70C I = industrial ....................................................... -40C to 85C Storage Temperature .................................... -65C to + 150C Voltage on VCC to VSS ..........................................-0.5V to + 7V Voltage on VPP to VSS ........................................-0.5V to + 13V Voltage on Any Pin to VSS..................................... -0.5V to VCC + 0.5V Power Dissipation .............................................................. 1 W Note:
Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package.
Power Consumption Measurement
Since the introduction of the first C51 devices, every manufacturer made operating ICC measurements under reset, which made sense for the designs were the CPU was running under reset. In our new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That's why, while keeping measurements under Reset, we present a new way to measure the operating ICC: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE)
Ports 1, 3, 4 are disconnected, RST = VCC, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating ICC.
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DC Parameters for Standard Voltage
Table 61. DC Parameters in Standard Voltage TA = -40C to +85C; VSS = 0 V; VCC = 5V 10%
Symbol VIL VIH VIH1 VOL Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 3, 4.(6) Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ Max 0.2 VCC - 0.1 Unit V V V V V V V V V IOL = 100 A IOL = 1.6 mA IOL = 3.5 mA IOH = -10 A IOH = -30 A IOH = -60 A Test Conditions
VCC + 0.5 VCC + 0.5
0.3 0.45 1.0
VOH
Output High Voltage, ports 1, 3, 4.(6) mode pseudo bi-directional
VCC - 0.3 VCC - 0.7 VCC - 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5
6 50 90
(5)
VCC = 5V 10%
IOH = -100 A IOH = -1.6 mA IOH = -3.2 mA
Output High Voltage, ports 1, 3, 4.(6) VOH2 mode Push pull
V V V M 200 -50 TBD 10 -650 10 k A A A pF A
VCC = 5V 10%
Off impedance, ports 1, 3, 4. RRST IIL ILI ITL CIO IPD ICC under RESET Power Supply Current Maximum values, X1 mode: (7) RST Pullup Resistor Logical 0 Input Current ports 1, 3 and 4 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 3, 4 Capacitance of I/O Buffer Power Down Current to be confirmed
VIN = 0.45V, port 1 & 3 VIN = 0.45V, port 4 0.45V < VIN < VCC VIN = 2.0V Fc = 1 MHz TA = 25C 2.0V < VCC < 5.5V
(3)
20 (5)
50 3+ 0.4 Freq (MHz) at 12MHz 5.8 at 16MHz 7.4
to be confirmed
mA
VCC = 5.5V (1)
ICC operating
Power Supply Current Maximum values, X1 mode: (7)
to be confirmed
3 + 0.6 Freq (MHz) at 12MHz 10.2 at 16MHz 12.6
mA
VCC = 5.5V(8)
ICC idle ICC operating VRET
Power Supply Current Maximum values, X1 mode: (7)
to be confirmed
3 + 0.3 Freq (MHz) at 12MHz 3.9 at 16MHz 5.1
mA
VCC = 5.5V(2) VCC = 5.5V(8),
Power Supply Current OSCB Supply voltage during power down mode 2
to be confirmed
6
mA V
at 12MHz
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DC Parameters for Low Voltage
Table 62. DC Parameters in Standard Voltage TA = -40C to +85C; VSS = 0V; VCC = 2.7 to 5.5V
Symbol VIL VIH VIH1 VOL Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 3, 4.(6) Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ Max 0.2 VCC - 0.1 Unit V V V V V V V V V V V V 6 50 90
(5)
Test Conditions
VCC + 0.5 VCC + 0.5
0.3 0.45 1.0
IOL = 100 A IOL = 0.8mA IOL = 1.6mA IOH = -10 A IOH = -30 A IOH = -60 A IOH = -100 A IOH = -0.8 mA IOH = -1.6 mA
VOH
Output High Voltage, ports 1, 3, 4.(6) mode pseudo bidirectionnel Output High Voltage, ports 1, 3, 4.(6) mode Push-pull Off impedance, ports 1, 3, 4.
VCC - 0.3 VCC - 0.7 VCC - 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5
VOH2
M 200 -50 TBD 10 -650 10 k A A A pF A VIN = 0.45V, port 1 & 3 VIN = 0.45V, port 4 0.45V < VIN < VCC VIN = 2.0V Fc = 1 MHz TA = 25C 2.0V < VCC < 5.5V
(3)
RRST IIL ILI ITL CIO IPD ICC under RESET
RST Pull-up Resistor Logical 0 Input Current ports 1, 3 and 4 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 3, 4 Capacitance of I/O Buffer Power Down Current
to be confirmed
20(5)
50 1.5+ 0.2 Freq (MHz) at 12 MHz 3.4 at 16 MHz 4.2
Power Supply Current Maximum values, X1 mode:
(7)
to be confirmed
mA
VCC = 3.3V(1)
ICC operating
Power Supply Current Maximum values, X1 mode:
(7)
to be confirmed
1.5 + 0.3 Freq (MHz) at 12 MHz 5.1 at 16 MHz 6.3
mA
VCC = 3.3V(8)
ICC idle ICC operating VRET
Power Supply Current Maximum values, X1 mode:
(7)
to be confirmed
1.5 + 0.15 Freq (MHz) at 12 MHz 2 at 16 MHz 2.6
mA
VCC = 3.3V(2) VCC = 3.3V(8),
at 12 MHz
Power Supply Current OSCB Supply voltage during power down mode 2
to be confirmed
3
mA V
Notes:
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 36.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; VPP = RST = VCC. ICC would be slightly higher if a crystal oscillator used 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Vpp = RST = VSS (see Figure 34.). 3. Power Down ICC is measured with all output pins disconnected; VPP = VSS; XTAL2 NC.; RST = VSS (see Figure 35.). 4. Not Applicable.
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5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 36.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; RST/VPP= VCC;. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst cas
Figure 32. VCC Test Condition, Under Reset VCC ICC VCC
RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS
All other pins are disconnected.
Figure 33. Operating ICC Test Condition VCC ICC
Reset = VSS after a high pulse during at least 24 clock cycles
VCC
VCC RST
All other pins are disconnected.
(NC) CLOCK SIGNAL
XTAL2 XTAL1 VSS
Figure 34. ICC Test Condition, Idle Mode VCC ICC
Reset = VSS after a high pulse during at least 24 clock cycles
VCC
VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS
All other pins are disconnected.
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Figure 35. ICC Test Condition, Power-down Mode VCC ICC VCC
Reset = VSS after a high pulse during at least 24 clock cycles
VCC RST XTAL2 XTAL1 VSS
All other pins are disconnected.
Figure 36. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.7VCC
0.2VCC-0.1 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns.
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DC Parameters for A/D Converter
TA = 0C to +70C; VSS = 0 V; VCC = 2.7V to 5.5V TA = -40C to +85C; VSS = 0 V; VCC = 2.7V to 5.5V Table 63. DC Parameters
Symbol Parameter Resolution AVIN RREF CAI Analog input voltage Resistance between Vref and VSS Analog input Capacitance Integral non-linearity Differential non-linearity Offset error -2 VSS - 0.2 13 18 60 1 0.5 2 1 2 Min Typ 10 Max Unit bit Test Conditions
VCC + 0.2
24
V K pF lsb lsb lsb During sampling 0.9 VCC< VREF <
VCC VCC
0.9 VCC< VREF < 0.9 VCC< VREF <
VCC
For 10 bit resolution at maximum speed
Input source impedance
1
K
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AC Parameters
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "t" (that stands for Time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TXHDV = Time from clock rising edge to input data valid. TA = -40C to +85C (industrial temperature range); VSS = 0V; 2.7V < VCC < 5.5V ; -L range. Table 64. gives the maximum applicable load capacitance for Port 1, 3 and 4. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 64. Load Capacitance Versus Speed Range, in pF
-L Port 1, 3 & 4 80
Table 66, Table 69 and Table 72 give the description of each AC symbols. Table 67, Table 70 and Table 73 give for each range the AC parameter. Table 68, Table 71 and Table 74. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need ( -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 65. Max frequency for Derating Formula Regarding the Speed Grade
-L X1 mode, VCC = 5V Freq (MHz) T (ns) 40 25 -L X2 mode, VCC = 5V 33 30 -L X1 mode, VCC = 3V 40 25 -L X2 mode, VCC = 3V 20 50
Example: TXHDV in X2 mode for a -L part at 20 MHz (T = 1/20E6 = 50 ns): x = 133 (Table 74) T = 50ns TXHDV = 5T - x = 5 x 50 - 133 = 117 ns
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External Program Memory Characteristic Table 66. Symbol Description
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ Parameter Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float
Table 67. AC Parameters for Fix Clock
Speed -L X2 Mode VCC = 5V
Min 33 25 4 4 45 9 35 25 0 12 53 10 0 20 95 10 17 60 50 0 10 80 10 Max
-L Standard Mode VCC = 5V
Min 25 42 12 12 78 Max
-L X2 Mode VCC = 3 V
Min 50 35 5 5 65 10 50 30 Max
-L Standard Mode VCC = 3V
Min 33 52 13 13 98 18 75 55 0 18 122 10 Max
Units
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ
ns ns ns ns ns ns ns ns ns ns ns ns
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Table 68. AC Parameters for a Variable Clock: Derating Formula
Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x -L X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x -L
VCC = 5V
8 13 13 22 8 15 25 0 5 30 10
VCC = 3V
15 20 20 35 15 25 45 0 15 45 10
Units ns ns ns ns ns ns ns ns ns ns ns
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External Program Memory Read Cycle Figure 37. External Program Memory Read Cycle
12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ
External Data Memory Characteristics
Table 69. Symbol Description
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold after RD Data Float after RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold after WR RD Low to Address Float RD or WR High to ALE high
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Table 70. AC Parameters for a Fix Clock
-l X2 Mode VCC = 5v
Min 85 85 60 0 18 98 100 30 47 7 107 9 0 7 27 15 70 55 80 15 165 17 0 35 5 0 35 165 175 95 45 70 5 155 109 0 45 13 Max
Speed
-l Standard Mode VCC = 5v
Min 135 135 102 Max
-l X2 Mode VCC = 3 V
Min 125 125 95 0 25 155 160 105 Max
-l Standard Mode VCC = 3v
Min 175 175 137 0 42 222 235 70 103 13 213 16 0 53 130 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH
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Table 71. AC Parameters for a Variable Clock: Derating Formula
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x -L X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x -L
VCC = 5V
15 15 23 0 15 35 50 20 20 20 10 10 8 0 10 10
VCC = 3V
25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
External Data Memory Write Cycle Figure 38. External Data Memory Write Cycle
ALE TWHLH
PSEN
TLLWL
TWLWH
WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX
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External Data Memory Read Cycle Figure 39. External Data Memory Read Cycle
ALE TLLDV TWHLH
PSEN
TLLWL TRLDV
TRLRH
RD TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TRLAZ ADDRESS A8-A15 OR SFR P2 TAVDV TRHDX DATA IN
TRHDZ
Serial Port Timing - Shift Register Mode
Table 72. Symbol Description
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Table 73. AC Parameters for a Fix Clock
-L (VCC=5V) X2 Mode 33 MHz Speed Symbol TXLXL TQVHX TXHQX TXHDX TXHDV 66 MHz Equiv. Min 180 100 10 0 17 Max -L (VCC=5V) Standard Mode 40 MHz Min 300 200 30 0 117 Max -L (VCC=3V) X2 Mode 33 MHz 66 MHz Equiv. Min 300 200 30 0 17 Max -L (VCC=3V) Standard Mode 40 MHz Min 300 200 30 0 117 Max Units ns ns ns ns ns
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Table 74. AC Parameters for a Variable Clock: Derating Formula
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T - x 2T-x x 10 T - x X2 Clock 6T 5T-x T-x x 5 T- x 50 20 0 133 50 20 0 133 -L (VCC = 5V) -L (VCC = 3V) Units ns ns ns ns ns
Shift Register Timing Waveforms Figure 40. Shift Register Timing Waveforms
INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV
VALID VALID
0
1
2
3
4
5
6
7
8
TXHQX 1 2 TXHDX
VALID VALID VALID VALID VALID
3
4
5
6
7 SET TI
VALID
SET RI
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EPROM Programming and Verification Characteristics
TA = 21C to 27C; VSS = 0V; VCC = 5V 10% while programming. VCC = operating range while verifying. Table 75. EEPROM Programming and Verification Characteristics
Symbol VPP IPP 1/TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low 4 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 10 10 90 110 48 TCLCL 48 TCLCL 0 48 TCLCL s s s Min 12.5 Max 13 75 6 Units V mA MHz
Data Hold after PROG
(Enable) High to VPP VPP Setup to PROG Low
VPP Hold after PROG
PROG Width Address to Valid Data ENABLE Low to Data Valid Data Float after ENABLE
EPROM Programming and Verification Waveforms Figure 41. EPROM Programming and Verification Waveforms
PROGRAMMING P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* P P0 TDVGL TAVGL ALE/PROG TSHGL TGLGH DATA IN TGHDX TGHAX TGHSL VPP TEHSH ADDRESS VERIFICATION ADDRESS TAVQV DATA OUT
EA/VPP CONTROL SIGNALS (ENABLE)
VCC
VCC
TELQV TEHQZ
* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5
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External Clock Drive Characteristics (XTAL1)
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Parameter Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Min 25 5 5 5 5 60 Max Units ns ns ns ns ns %
External Clock Drive Waveforms Figure 42. External Clock Drive Waveforms
VCC-0.5V
0.45V 0.7VCC 0.2VCC-0.1 V TCHCL TCLCX TCLCL TCHCX TCLCH
A/D Converter
Symbol Parameter Min Typ Max Units Clock periods (1 for sampling, 10 for conversion) s 350 8
(1)
TConv
Conversion time
11
TSetup Fconv_ck
Setup time Clock Conversion frequency Sampling frequency
4
kHz kHz
32
Note:
1. For 10 bits resolution
AC Testing Input/Output Waveforms Figure 43. AC Testing Input/Output Waveforms
VCC-0.5V
INPUT/OUTPUT 0.45V 0.2VCC+0.9 0.2VCC-0.1
AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurement are made at VIH min for a logic "1" and VIL max for a logic "0".
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Float Waveforms Figure 44. Float Waveforms
FLOAT VOH-0.1 V VOL+0.1 V VLOAD VLOAD+0.1 V VLOAD-0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
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Figure 45. Clock Waveforms
INTERNAL CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION STATE4 P1P2 STATE5 P1P2 STATE6 P1P2 STATE1 P1P2 STATE2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2
P2 (EXT) READ CYCLE RD
INDICATES ADDRESS TRANSITIONS
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt FLOAT P2 WRITE CYCLE WR P0 DPL OR Rt OUT DATA OUT P2 PORT OPERATION OLD DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED NEW DATA P0 PINS SAMPLED INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION
RXD SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
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Ordering Information
Table 76. Maximum Clock Frequency
Code Standard Mode, oscillator frequency Standard Mode, internal frequency X2 Mode, oscillator frequency (VCC = 5V) X2 Mode, internal equivalent frequency (VCC = 5V) X2 Mode, oscillator frequency (VCC= 3V) X2 Mode, internal equivalent frequency (VCC = 3V) -L 40 40 33 66 20 40 Unit MHz
MHz
MHz
Table 77. Possible Order Entries
Part Number AT80C5112-S3SIL AT80C5112-S3RIL AT80C5112-RKTIL AT80C5112-RKRIL AT83C5112-S3SIL AT83C5112-S3RIL AT83C5112-RKTIL AT83C5112-RKRIL AT87C5112-S3SIL AT87C5112-S3RIL AT87C5112-RKTIL AT87C5112-RKRIL Memory Size ROMless ROMless ROMless ROMless 8K ROM 8K ROM 8K ROM 8K ROM 8K OTP 8K OTP 8K OTP 8K OTP Supply Voltage 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V Temperature Range Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Max Frequency 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ 66 MHZ Package PLCC52 PLCC52 LQFP48 LQFP48 PLCC52 PLCC52 LQFP48 LQFP48 PLCC52 PLCC52 LQFP48 LQFP48 Packing Stick Tape & Reel Tray Tape & Reel Stick Tape & Reel Tray Tape & Reel Stick Tape & Reel Tray Tape & Reel
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Packaging Information
PLCC52
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LQFP48
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Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2003. All rights reserved. Atmel (R) and combinations thereof are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
4191B-8051-04/03 /xM

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